Cyber Secure and Resilient System-on-Chip using FPGA Dynamic Configuration (Internship) King Abdullah University of Science and Technology (KAUST)

Overview

 For this, programmable hardware is considered a tradeoff between software logic— fully flexible, slow, and mutable—and hard logic—fully rigid, fast, and immutable. We believe that there are promising opportunities to boost the resilience of the programmable platforms against faults and intrusions, although immutability is slightly reduced [SoC]. 

This Cyber Secure and Resilient System-on-Chip using FPGA Dynamic Configuration (Internship) project from King Abdullah University of Science and Technology (KAUST) explores the techniques to use FPGA dynamic reconfiguration to boost the resilience of a System-on-Chip [Samsara]. 

This can be done through changing the FPGA infrastructure itself, e.g., elastic dynamic partitioning, dimorph sizes and shapes, replicate partitions, etc.; or through changing the IP logic running on, e.g., dynamic Byzantine intrusion resilience protocols [Samsara], adaptive ML detection protocols, or loading different IPs as a threat response. 

Key Facts

The intern will be working on one of these tasks. [SoC] Shoker, Ali, Paulo Esteves-Verissimo, and Marcus Völp. "The path to fault-and intrusion-resilient manycore systems on a chip." 2023 53rd Annual IEEE/IFIP International Conference on Dependable Systems and Networks-Supplemental Volume (DSN-S). IEEE, 2023. [Samsara] Pinto Gouveia, Inês, et al. "Resilient and Secure Programmable System-on-Chip Accelerator Offload." arXiv e-prints (2024): arXiv-2406.