Cyber Secure and Resilient System-on-Chip using FPGA Dynamic Configuration (Internship) King Abdullah University of Science and Technology (KAUST)

Overview

Despite these facts, there is a continuous wave of relaxing these “rigid” hardware designs through introducing programmable (including reconfigurable and adaptable) fabric. The main reason is to improve hardware flexibility and compatibility, i.e., making them application-agnostic, and to facilitate the daunting design verification process prior to fabrication, hence cutting off fabrication costs thereof. For this, programmable hardware is considered a tradeoff between software logic— fully flexible, slow, and mutable—and hard logic—fully rigid, fast, and immutable.

Key Facts

This Cyber Secure and Resilient System-on-Chip using FPGA Dynamic Configuration (Internship) project from King Abdullah University of Science and Technology (KAUST) explores the techniques to use FPGA dynamic reconfiguration to boost the resilience of a System-on-Chip [Samsara]. This can be done through changing the FPGA infrastructure itself, e.g., elastic dynamic partitioning, dimorph sizes and shapes, replicate partitions, etc.; or through changing the IP logic running on, e.g., dynamic Byzantine intrusion resilience protocols [Samsara], adaptive ML detection protocols, or loading different IPs as a threat response.

Recommended Student Background

• FPGA

• Hardware Security

• System Architecture

• Blockchain